Nevertheless, the reduction in geometrical sizes has resulted in an exponential increase in leak currents between source and drain, also referred to as below-threshold currents, present even when the transistor is cut off: for the latest sub-micron generations, this leak current has become a source of energy loss that cannot be left out of account.
Therefore, it has become necessary to decrease the effect of these leak currents, meaning reducing the power supply voltages and transistor threshold voltages to a smaller proportion. The direct consequence of this is that the electric field applied across the terminals of the gate dielectric is greater. This exposes the dielectric to greater stress, in particular at the point where the gate overhangs the drain and/or source. if we consider the example of an NMOS transistor, in the conducting state, its drain and gate are polarized at Vdd and its source at Vm. If we refer to the two logic power supply voltage levels as being Vdd and Vm as illustrated in FIG. 1a: the dielectric is affected by a stress at the point where the gate overhangs the source. In the cut-off state, the gate is brought to Vm while the polarization of the drain and source remain unchanged as illustrated in FIG. 1b: The dielectric is affected by a stress at the point where the gate overhangs the drain. For a PMOS transistor, the position of drains d and sources s is reversed in the figures.
However, the recent predictions published in the document by James Stathis: “Gate Oxide Reliability for nanoscale CMOS”, International Symposium on Physical and Failure Analysis, pp 127-130, June 2005, demonstrate that by reducing the size of the transistors, a gate dielectric will tolerate an electrical field across its terminals of around 1 V per nanometer of thickness.
Accordingly, reliability is decreased in thin dielectric transistors used in logic circuits, especially fast logic circuits, powered by a polarizing voltage at their gates, source and drain, corresponding to the logic supply voltage levels of the circuit.
The stress affecting the gate dielectric is increased even more in the power transistors used in the analog stages of electronic circuits, controlled by higher voltages than at the logic power supply voltage, causing these transistors to become highly conductive or highly cut-off. For instance, let us consider the power transistors used as power supply cut-off devices for all or part of an electronic circuit in stand-by mode to reduce the stand-by mode leak current. SCCMOS (“Super Cut-off CMOS”) transistors are an example of the transistors used for this kind of function. A description is to be found in particular in the following publication: H. Kawaguchi et al., “A super Cut-Off CMOS (SCCMOS), Scheme for 0.5 V Supply Voltage with Picoampere Stand-by Current”, IEEE Journal of Solid State Circuits, vol. 35 No 10, pp 1498-1501, October 2000. They are characterised by their capability of conducting high current in the conductive mode, low leak current in the cut-off state, for an optimal occupied circuit area (with respect to the current in the conductive state).
For this kind of use, in stand-by mode, the transistor is blocked and the transistor gate is inverse “super-polarised”, producing leak current beneath the minimum threshold. In reality, the leak current below the threshold decreases exponentially when more negative polarization is applied to the gate for an NMOS or more positive polarization for a PMOS. Inverse super-polarization refers to the polarization of the gate at a lower voltage than the most negative terminal of the logic supply voltage of the circuit for an NMOS transistor or higher than the most positive supply terminal of the logic supply voltage for a PMOS circuit.
This mode of inverse polarization produces increased stress in the gate dielectric, in the example, more specifically at the point where the gate overhangs the drain so that the drain gate voltage becomes greater than the logic supply voltage. This results in the reduction of the power transistor reliability.
Accordingly, generally speaking, the “miniaturisation” of field-effect transistors reduces their reliability and subsequently the duration of electronic integrated circuits using this type of transistor. This means that the stakes are high, especially for fast logic and for every type “portable” application.
One objective of the present invention is to increase the reliability of field-effect transistors in this way.
It has been seen that in thin dielectric arrangements, stress does not generate the abrupt breakdown of the dielectric as occurs in thicker dielectrics but, on the contrary, leads to a phenomenon of soft breakdown. This phenomenon of soft breakdown is explained in the following publication: Depas et al. “Soft Breakdown of Ultra-thin Gate Oxide Layers”, IEEE Transactions on Electron devices Vol. 43, no. 3, September 1996. It is illustrated in FIG. 2, using the example of an MOS technology transistor on a silicon substrate and having a silicon oxide gate dielectric. The ordinates represent the gate voltage which is applied to maintain constant current through the dielectric. Initially, the applied voltage decreases slowly: this part of the curve up to the SBD point corresponds to the generation of faults (carrier traps) in the SiO2 dielectric and at the substrate/dielectric Si/Si02 interface due to the tunnel injection of electrons in a strong electric field. When, locally, these faults reach sufficient density, a conduction path is formed: this is the first breakdown (SBD point in the figure). This initial breakdown can be followed by other breakdowns. When the conduction path or paths are widened by thermal effects and join one another, the rate of change of the current through the dielectric becomes very high until the transistor switches out (BD point).
The soft breakdown phenomenon as observed allows the detection or following of the aging of the dielectric, before reaching the final breakdown point BD.